A fast simulation-driven pre-fabrication workflow for transmon-based superconducting quantum chips

Details

Supervisors

Melinte, Sorin

Faculty

Ecole polytechnique de Louvain

Degree label

Master [120] : ingénieur civil physicien, à finalité spécialisée

Abstract

enScalable fault-tolerant quantum computing requires hardware that faithfully translates designed Hamiltonians into physical devices. This goal remains challenged by fabrication induced deviations in qubit frequencies, couplings, and coherence times. Superconducting transmons in cavity-QED architectures represent a leading platform, yet conventional design–build–test cycles impose prohibitive costs and delays due to their reliance on postfabrication tuning and characterization. This thesis introduces a simulation-driven, pre fabrication workflow that links chip layout directly to circuit-level performance through the lumped-oscillator model (LOM). The conception flow start with analytically-derived resonator parameters that seed initial layout, from which capacitance and inductance values are extracted via Ansys Q3D for LOM-based quantization of qubit frequencies, anharmonicities, dispersive shifts, and coupling rates. Then, structured parametric sweeps over connector length, pad dimensions, pad gap, and Josephson inductance map the dominant geometric sensitivities governing coherence, frequency, and coupling strength. Complementary conformal-mapping calculations estimate external quality factor, photon lifetime, and linewidth for feedline coupling geometries. Additionaly, HFSS eigenmode simulations validate preservation of the intended modal structure, establishing a robust starting point for forthcoming energy-participation-ratio (EPR) analysis. The resulting parameter response maps and tolerance windows provide actionable priors for design refinement, reduce reliance on iterative prototyping, and offer a transferable methodology for accelerating the development of scalable superconducting-qubit processors.