Porous silicon integration in bulk CMOS with a post-process approach for RF performance enhancement

Details

Supervisors

Raskin, Jean-Pierre

Faculty

Ecole polytechnique de Louvain

Degree label

Master [120] : ingénieur civil électricien, à finalité spécialisée

Abstract

enBulk CMOS technologies remain attractive for RF and millimeter-wave integrated circuits because of their low cost, maturity, and compatibility with large-scale integration. However, standard-resistivity silicon substrates introduce RF losses, capacitive coupling, and substrate-induced parasitics. Porous silicon (PSi) is a promising substrate-engineering solution because of its high effective resistivity and low effective permittivity. With a back-side post-process approach, PSi can be formed after front-end fabrication and locally introduced below RF structures. While this strategy has been demonstrated on SOI substrates, its transfer to bulk CMOS requires a reliable stopping mechanism to prevent the porous front from reaching the front-side devices. This thesis investigates the use of P- and N-doped regions as a bulk-compatible etch-stop strategy for post-process PSi integration. The proposed approach relies on the reduced porosification of N-type regions and on the depletion regions formed at PN junctions. Experimental observations from porosified PN etch-stop layer candidates show that these patterns can influence the porous front, but also reveal significant non-uniformity along the porous pocket. To interpret these effects, two-dimensional and three-dimensional COMSOL models are developed. The 2D simulations isolate the effect of local resistivity profiles and show that PN patterns can slow down the porous front. The 3D simulations demonstrate that the finite length of the back-side opening and the metallic grid geometry can induce longitudinal non-uniformity. Modified electrode geometries are therefore proposed to reduce this effect and improve the uniformity of the residual silicon thickness. Overall, this work shows that P- and N-doped regions are a plausible route toward bulk-compatible post-process PSi integration. However, the final morphology results from a coupling between etch-stop layer design and three-dimensional layout geometry. Further work is required to refine the electrochemical model and experimentally validate optimized doping and grid geometries.