Comparison of Self-Heating Extraction Techniques in FD-SOI Transistors down to 4 K

Details

Supervisors

Raskin, Jean-Pierre

Faculty

Ecole polytechnique de Louvain

Degree label

Master [120] : ingénieur civil électricien, à finalité spécialisée

Abstract

Self-heating is structural in FD-SOI technologies: the buried oxide that isolates the transistor electrically also blocks its main heat evacuation path, and the effect worsens at cryogenic temperatures, where cryo-CMOS power budgets are tightest. This work compares, on a single advanced FD-SOI device design, the two electrical thermometries applicable to standard test structures: DC gate resistance thermometry, which reads the gate, and RF thermometry, which reads the channel through the frequency response of the output conductance. Both are built, validated and bounded on a 4-295 K campaign: gate thermometry covers the whole range but loses its sensitivity below about 40 K, while RF thermometry is reliable only over 77-295 K and in strong inversion. Compared at matched dissipated power over their 77-295 K overlap, the two techniques do not return the same thermal resistance: the channel heats markedly more than the gate reads, by a factor close to two that increases on cooling, reproduced on every die measured. A reduced thermal network accounts for the direction of the gap, since RF thermometry reads the channel while gate thermometry reads a gate node cooled through the back-end, but not for its full magnitude. The gate temperature is thus not the device temperature: read together, the two thermometers measure the thermal coupling between the channel and its gate.