FPGA acceleration of an USRP-based OFDM chain for integrated sensing and communication

Prieels, Quentin
(2025)

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Details

Supervisors
Andraud, Martin ; Louveaux, Jérôme
Faculty
Ecole polytechnique de Louvain
Degree label
Master [120] : ingénieur civil en informatique, à finalité spécialisée
Abstract
enIntegrated Sensing And Communication (ISAC) systems are promising systems for a wide variety of domains, such as autonomous driving and healthcare. They enable a single frame to serve both communication and radar functions simultaneously. This work focuses on accelerating the receiver chain of an Orthogonal Frequency-Division Multiplexing (OFDM)-based ISAC system, implemented using the Universal Software Radio Peripheral (USRP). By leveraging the internal Field Programmable Gate Array (FPGA) of the USRP, key operations like timing synchronization and OFDM demodulation are offloaded to hardware. To efficiently implement these hardware operations, the RF Network-on-Chip (RFNoC) framework is employed. As a result, the improved system achieves an 84\% improvement in processing speed. This work represents a step toward a real-time implementation of the receiver chain.