Characterization, Modeling, and Simulation of Fully Depleted Silicon-on-Insulator Transistors in Harsh Environments: High Temperature Study

Details

Supervisors

Raskin, Jean-Pierre

Faculty

Ecole polytechnique de Louvain

Degree label

Master [120] : ingénieur civil électricien, à finalité spécialisée

Abstract

enOperating electronic components in harsh environment (e.g. automotive, aerospace) and low-power Internet of Things (IoT) applications, requires high thermal stability under severe stress. However, standard foundry models often fail to predict extreme thermal degradation, and the physical mechanisms behind high-temperature loss within 4-port back-gate networks remain insufficiently mapped. This thesis investigates the physical origins of temperature-induced degradation in DC and RF performance of 22 nm Fully-Depleted Silicon-on-Insulator (22FDX, registered trademark) MOSFETs across a 30 to 170 °C thermal gradient. A core objective is evaluating the back-gate node to understand its DC thermal leakage dependence, and modeling its wideband 4-port back-gate/substrate network to predict intrinsic RF figures of merit (FoMs). A combined approach of characterization, physical modeling, and simulation was employed. Intrinsic device behavior was isolated via DC and RF de-embedding methods. DC measurements were benchmarked against Technology Computer-Aided Design (TCAD) simulations including Hydrodynamic and advanced mobility models for short-channel energy transport. For RF analysis, a back-gate self-heating-free extraction in the cold-FET regime (\(V_{DS} = 0\) V) enabled the development of a lumped 4-port small-signal equivalent circuit (SSEC), benchmarked against foundry Process Design Kit. DC analysis revealed high digital thermal stability, with a threshold voltage (\(V_{TH}\)) drift of 0.45–0.50 mV/°C. However, at 110 °C, short and narrow channels (\(L_{g} = 20\) nm, \(W_{f} \le 1\) \(\mu\)m) exhibited anomalous subthreshold drain current saturation, hypothesized to stem from localized front-gate oxide soft breakdown. At higher temperatures, localized Joule heating permanently damaged the silicon channel. Back-gate leakage increased exponentially to nanoampere levels from intrinsic carrier thermal generation, while front-gate and drain capacitive coupling impacted low-power IoT constraints. In the RF domain, the 4-port SSEC showed that front-gate performance is isolated from the substrate, achieving an intrinsic transition frequency (\(f_{T,f}\)) of 330.7 GHz and maximum oscillation frequency (\(f_{max,f}\)) of 320.5 GHz. Conversely, parasitic substrate capacitances (\(C_{nwpsub1}\) and \(C_{nwpsub2}\)) significantly attenuated back-gate RF metrics, with negligible resistive impact. Overall, RF FoMs proved highly dependent on front and back transconductances, inherently degraded by temperature and parasitic series resistances. To mitigate high-temperature leakage in ultra-low-power IoT designs, a novel electrostatic leakage model is proposed for integration into compact BSIM-IMG frameworks. Additionally, the calibrated TCAD models decouple the physical origins of thermal degradation, while the back-gate/substrate SSEC offers insights for device reliability. Finally, formalized analytical RF FoM definitions identify critical bottlenecks, providing a foundation for optimizing back-gate RF metrics where prior studies remain limited.