Development of an FPGA Processor with RISC-V Architecture for Aerospace Applications

Details

Supervisors

Andraud, Martin ; Bastin, Brieuc

Faculty

Ecole polytechnique de Louvain

Degree label

Master [120] : ingénieur civil en informatique, à finalité spécialisée

Abstract

enSABCA, a Belgian aerospace and defense company, develops a custom soft-core processor known as the Control Loop Processor (CLP). The CLP powers a range of systems found on European launchers such as Vega-C and Ariane 6, as well as on commercial aircraft. The CLP’s instruction set, however, is proprietary, and the software stack has to be written in assembly. As a result, software development is slow, code reuse is limited, and the platform is increasingly difficult to evolve. This thesis investigates whether the compute behavior and the existing peripheral collection of the CLP can be preserved while replacing the custom central processing unit with a processor based on the open RISC-V instruction set architecture. We review the open-source RISC-V landscape against a set of criteria derived from SABCA’s industrial context, and we select the NEORV32 soft-core processor as the candidate that best fits the constraints. We then integrate the NEORV32 inside the existing CLP_SA5 VHDL package without modifying its peripherals, by extending the processor with two missing single-precision floating-point operations (fdiv.s and fsqrt.s) and by designing an XBUS-to-APB bridge that exposes the original APB-connected peripherals and systems (timers, GPIOs, PWMs, ADC interface) as memory-mapped regions inside the NEORV32 address space. On the software side, we develop a small Hardware Abstraction Layer in C, port a representative slice of the SABCA macro library and translate part of the Z40 thrust-vector-control flight software from CLP assembly to C. The resulting platform is validated along two complementary axes. First, the C control loops are compared block-by-block against the original Simulink reference model using the same input vectors. Second, the software is deployed on a Microchip IGLOO2 development board connected to a power-electronics board driving a real Z09 motor, and the closed-loop behavior is captured through APB Real-Time Background Tracer (RTBT) recordings. We show that the resulting system can drive the motor in closed loop across a representative range of speed references and dynamic profiles. The contributions of this thesis are therefore threefold. We provide an in-depth analysis of the integration cost of an open-source RISC-V core inside an industrial FPGA platform, we deliver a portable C-based re-implementation of a representative subset of the flight software, and we demonstrate that the migration is capable of performing the main duty of the CLP, while opening the way to faster software development and long-term maintainability.