Hardware implementation of unlimited sampling for the analog-to-digital conversion of high dynamic range signals

Details

Supervisors

Flandre, Denis

Faculty

Ecole polytechnique de Louvain

Degree label

Master [120] : ingénieur civil électricien, à finalité spécialisée

Abstract

enNearly every device interacting with real-world information relies on an Analog-to-Digital Converter (ADC), whose role is to convert analog signals into discrete binary values. However, when the input signal exceeds the limited dynamic range of the ADC, saturation occurs and the signal becomes clipped, resulting in a significant loss of information. To address this limitation, the Unlimited Sampling (US) framework has emerged in recent years. By combining a Modulo-ADC with dedicated reconstruction algorithms, the input signal can be folded into a fixed dynamic range compatible with the ADC operating range, while still allowing recovery of the original signal from its modulo samples. This work investigates a hardware implementation of a modulo-ADC architecture with the objective of maximizing both the allowable input dynamic range and the maximum input frequency. Existing implementations proposed in the literature are first reviewed in order to design a new hardware architecture acting as a front-end stage placed before a conventional ADC. The proposed system relies on comparators that monitor the signal amplitude and detect threshold crossings, while a dedicated control block generates the correction signals required to wrap the input back into the desired range whenever necessary. The implementation of each block is described in detail, including the underlying theory, component selection and sizing, as well as LTspice simulations. Once the PCB is fabricated and assembled, the functional behavior of the prototype is verified experimentally and several performance measurements are conducted. For this first prototype, the input range is limited to 9.2V peak-to-peak due to the supply voltage constraints of the selected components. With folding thresholds fixed to ±1V, the system is capable of performing up to two folds while enabling successful post-processing reconstruction of the original signal. The measured folding delay is approximately 200ns, allowing maximum input frequencies ranging from 75kHz for a 9V peak-to-peak input signal up to 270kHz for a 3V peak-to-peak input signal, while maintaining a folded output contained within the interval [−1.25, 1.25]V. Finally, several improvements are proposed to further increase both the achievable dynamic range and the maximum operating frequency, mainly through the replacement of certain components. The obtained results confirm the feasibility of a hardware implementation of a modulo-ADC for the acquisition and processing of high-dynamic-range signals, while also highlighting challenges related to propagation delays and supply voltage limitations.