A study of vectorized and SIMD batch processing techniques in high-speed packet processing frameworks

Details

Supervisors

Barbette, Tom

Faculty

Ecole polytechnique de Louvain

Degree label

Master [120] en sciences informatiques, à finalité spécialisée

Abstract

enRecent years have witnessed the popularization of software-based networking, due to its high flexibility and ease of development. This implies that network functions had to be ported over to software implementations. These new routers typically combine elementary processing elements to form a packet processing pipeline. With ever-increasing network speeds, several techniques have been developed to leverage each CPU cycle efficiently. Amongst these, there is packet batching, allowing to benefit from grouped operations to reduce overhead. CPU manufacturers have also developed Single Instruction Multiple Data frameworks, such as AVX. These allow to increase the amount of data processed simultaneously in the CPU pipeline. Some software routers have incorporated this technology to a varying degree in their codebase. In this work, we examine how different implementations of these technologies impact the throughput and latency of FastClick, a high-speed packet processing framework. Specifically, we compare the linked-list and vectorized batch processing approaches. The comparison also includes a variant with an element built with support for AVX. A thorough analysis under different scenarios is given, highlighting the strengths and weaknesses of each technique. It is shown that vectorized batches see an improvement of ~2.7% compared to linked-list packet batches in a simple TTL-decrementing IP application. It is also shown that AVX sees a 22.4% increased throughput, and an 8.6% decreased latency when chaining multiple AVX-enabled TTL-decrementing elements one after another.