Hardware accelerator design and algorithmic optimization for an ultra-low-power vagus nerve-based seizure detection system

(2026)

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Abstract
Treating drug-resistant epilepsy using implantable neurostimulation devices requires reliable continuous monitoring solutions that are compatible with stringent power constraints. Vagus nerve electroneurography (VENG) has recently emerged as a promising signal source for seizure detection. However, existing approaches remain limited by their power consumption. This work aims to design an ultra-low-power seizure detection system by improving and extending a previously proposed VENG-based solution. To this end, algorithmic/software optimizations and hardware acceleration are jointly explored. The original normalized cross-correlation (NCC)-based template matching algorithm is adapted to better support hardware implementation, while software optimizations are introduced to reduce power consumption. In addition, several hardware architectures are investigated, leading to the design of a parallel-template NCC hardware accelerator. The proposed approach achieves a power consumption of 2.45 mW for a single-template software-only implementation of the seizure detection algorithm. Compared to prior work, this corresponds to a x4 reduction in execution time and a x3.77 reduction in power consumption. Furthermore, the introduced optimizations enable real-time processing of up to 7 templates instead of one. The hardware accelerator exhibits an estimated power consumption of 53.48 µW at 1 MHz while maintaining high computational accuracy. System-level projections on the BREWER platform indicate a total power consumption of 502.37 µW. These results demonstrate that efficient seizure detection under strict ultra-low-power constraints can be achieved through a co-design approach combining software optimizations and hardware acceleration, thereby paving the way toward practical implantable VENG-based monitoring systems.